1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device with a circuit generating a reset signal for equalizing the potentials of a pair of complementary bit lines connected to a static type random access memory (SRAM) cell. The device according to the present invention is used, for example, in an information system of a computer, an electronic apparatus, and the like.
2. Description of the Related Art
In a conventional semiconductor memory device, to reduce access time, i.e., a time taken to read data from a memory cell, a technique of equalizing the potentials of a pair of signal lines for transferring the complementary signal, for example a pair of bit lines, or a pair of data bus lines, connected to the memory cell in the non-selection state of the chip has been employed. In this case, the potentials of the pair of bit lines or data bus lines must be reliably reset or equalized irrespective of the length of the pulse width of an active low chip selection signal, which will be hereinafter referred to as a chip non-selection signal. In the known device, however, reset signals having a constant pulse width are generated in response to a change of the chip non-selection signal from high level to low level, irrespective of the length of the pulse width of the chip non-selection signal. Accordingly, where the pulse width of the chip non-selection signal is short, a serious problem arises in that the potentials of the pair of bit lines cannot be fully reset, and thus it takes a long time for the memory cell to reach the stand-by state, resulting in an increase of the access time.
On the other hand, to decrease the currents dissipated during the stand-by period of the memory cell, usually a switching transistor controlled by the chip non-selection signal is inserted into a circuit portion, where a steady direct current flows, of a decoder circuit and the like in the device, to bring the direct currents dissipated during the stand-by period to zero volt. As a result, the currents dissipated during the stand-by period can be decreased, and consist only of the very small currents which flow through load resistors in the memory cell. However, in a system using many such SRAM devices, a structure is often employed wherein address terminals of each SRAM device are connected to a common address bus and a desired SRAM device is selected through control of the chip non-selection signal. In this system, taking into consideration each of the SRAM devices, input signals to address signal terminals are changed during the stand-by period. As is well known, in a complementary metal oxide semiconductor (CMOS) circuit, the currents dissipated in the steady state are extremely small, but the currents dissipated when the input signal is changed at a high speed are considerably large. Thus, in the system of the above-mentioned structure, the currents dissipated in a first stage CMOS circuit having an input connected to address signal input terminals and a subsequent CMOS buffer circuit driven by the first stage CMOS circuit can become considerably large. Particularly, in an extremely large capacity SRAM device having a large number of address input terminals and a corresponding number of circuits, the currents dissipated in the entire first stage circuit and subsequent buffer circuit, which continually respond to the change of address, are extremely large, in contrast to the total currents dissipated during the stand-by period. To cope with this problem, the technique of chip selection (CS) first stage control has been heretofore employed.
In an example of the related art device using this CS first stage control, a CS buffer and an address buffer are provided, and the change of address signal is not transmitted to an internal circuit following the address buffer and including memory cells, so that the power dissipation can be decreased. However, when such a CS first stage control is effected, inevitably a delay occurs in the CS buffer, from the time when the chip non-selection signal is input, to the time when the address buffer is controlled.
Therefore, in the semiconductor memory device using the above-mentioned CS first stage control, when the pulse width of the chip non-selection signal is short, the potentials of the pair of bit lines cannot be fully reset, and thus it takes a long time for the memory cell to reach the stand-by state, and further, the delay time due to the CS first stage control is added thereto, resulting in a disadvantageous access operation, particularly in an access operation in a high speed SRAM device.